Next generation multi-media broadcast standards use encoded high-bandwidth streams of data to efficiently utilize the spectrum, at the cost of computation intensive processing. For battery powered portable devices this is challenging, as the energy source has limited capacity. By optimizing the computationally intensive kernels within an application, the energy consumption can be reduced significantly. A highly parallel Multi-processor System-on-Chip architecture is proposed, consisting of processors which communicate over Network-on-Chip via a Network Interface, a component that converts the communication protocols and synchronizes the processor and network.
With multiple processors on a single chip, the available processing power increases and the processors can be used simultaneously. Another advantage of using a multi-processor architecture besides parallel processing, is concurrency in computation and communication. To utilize this concurrency efficiently, the Network Interface should support this concurrency.
The programming model for such an architecture differs from conventional single processor systems. Partitioning of the applications into multiple concurrent threads is important to obtain high utilization of the computational resources. The application can be modeled as a set of independent kernels connected by communication channels, where kernels are mapped on processors, and communication channels are mapped on the Network-on-Chip. In this thesis, the design flow that enables modeling of streaming applications is discussed. The application model is based on a functional programming language, which has a strong resemblance with mathematics such that the application can be gradually translated from a mathematical specification to a partitioned realization. To verify the performance of a mapped application, a simulation model is created containing information about the application and architecture model.
To illustrate the efficiency of the presented Network Interface and to demonstrate the data flow modeling technique, two wireless communication receivers are discussed. One receiver is a Digital Radio Mondiale receiver for handheld devices, where energy-efficiency is a key design goal, and the other is a Digital Video Broadcast for Satellite receiver targeting at the car infotainment domain. Both receivers are implemented on the same Multi-processor System-on-Chip, to show that such architectures are flexible for running different applications.
Reference
Press articles For more information related to the Ph.D. thesis, two press articles were issued (by the EEMCS faculty and by the University of Twente). Republication of the articles was done by ScienceGuide, Nieuwsbank, Tweakers.net, Kicero, engineersonline.nl, Elektor, HET magazine (all in Dutch) and Slashdot.org, AlphaGalileo, ScienceDaily, Technology Daily (in English).
Research project
| Funding | STW |
| Duration | 01-03-2007 ~ 01-03-2011 |
| Staff | Gerard Smit, André Kokkeler, Jan Kuper, Kenneth Rovers, Marcel van de Burgwal |
| External | Eric Klumperink (EEMCS-ICD), Hans Schurer (Thales Nederland BV) |
| Partners | Integrated Circuit Design (ICD) group, University of Twente |
| Website | http://caes.ewi.utwente.nl/Research/?project=BeamForce |
Background Satellite receivers with a dish antenna receive signals that fall within the so-called beam of the antenna. Every antenna has a characteristic beam pattern, which is determined by the mechanical construction of the dish antenna. When using an array of antenna elements, the beam-pattern can also be defined electronically. Such beamforming can be realized via an antenna array combined with electronics, making the array direction sensitive via phase shifters or time delays. Beamforming is the basis for realizing smart antennas, which intelligently adapt their antenna beam pattern to the local environment, e.g. to maximize received signal quality and minimize interference.
Phased array beamforming
Beamforming is the basis for "smart antennas", which can intelligently adapt their beamform to the local conditions for reception.
"Smart antennas" can maximise the wanted signal and reject distortions.
These potential advantages can be exploited for many applications (radar, mobile communications, astronomy, but also for example consumer electronics).
However, a cheap generic platform for phased array beamforming is not available.
The phased array beamforming project researches the requirements and the design of a efficient, flexible and integrated architecture for beamforming.
We will explore the fundamental possibilities for beamforming, aimed at mixed analog/digital techniques, suitable for CMOS.
The underlying idea is a modular, tiled hierarchical array on multiple abstraction levels; from a tile with antenna and digital signal processing, to SoCs (System-on-Chip) with multiple tiles, to MSoCs (Multiple-SoCs) with multiple SoCs.
Problems of current systems are the small numbers (not generic), price (special process technology) and scalability (central processing).
The research questions consists of:
- what is a suitable hardware/software co-design with the different trade-offs,
- what does a flexible distributed computer architecture look like for the large amount of incoming data, and
- how can we guarantee a certain Quality of Service when tiles fail.
CMOS Beamforming Techniques
Until now, beamforming is mainly applied in military applications, and more recently in base stations for telecommunication.
Applications in consumer electronics are scarce, despite of the many potential advantages (see utilization summary).
This is because beamforming is typically implemented using specialized microwave and Radio Frequency (RF) technologies with hybrid module assembly techniques, and many RF-cables and connectors, unsuitable for cost-effective mass production.
For consumer electronics, a high level of integration, preferably in mainstream CMOS technology, is desired.
However, CMOS technology is also increasingly important for military and high-end telecom applications, because of the large amount of digital signal processing involved in smart antennas.
Thus a convergence in IC-technology for telecom, military and consumer applications can be observed, leading to the observation:
"If CMOS technology can, it will".
From a functionality, size and cost point of view, it would be very attractive to also realize the radio interface of a beamforming system in CMOS.
In this project we want to explore fundamental options for beamforming, aiming to find new mixed analog-digital beamforming techniques suitable for CMOS.
Concretely, we propose to study techniques suitable for satellite receivers in the 10-12GHz band.
This is scientifically very challenging, as virtually all known beamforming systems heavily rely on high quality RF components and on microwave structures with physical sizes related to the wavelength of the radio frequency.
At 10GHz the wavelength is 3cm, making microwave component sizes too large to fit on a CMOS chip.
Inductors can be realized but are not very attractive as they take large chip area and have relatively poor quality.
On the other hand, recent research shows that multi- GHz samplers are becoming feasible in CMOS, while jitter in samplers is less of a problem that often thought.
This might open the door to new CMOS compatible beamforming techniques, using no or only a few traditional RF components.
In this project we want to explore the possibilities for such techniques, focusing on the RF and mixed analog/digital signal processing.
2012
2011
Vector Modulator. Master's thesis, University of Twente.
2010
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2008
2007
Research project
| Funding | EU FP6 |
| Duration | 01-01-2004 ~ 01-01-2008 |
| Staff | Gerard Smit, Thijs Krol, Bert Molenkamp, Marcel van de Burgwal, Pascal Wolkotte, Lodewijk Smit, Paul Heysters |
| Partners | ASICenter, ATMEL, Dicas, Harman/Becker, IMEC, PACT, Thales, University of Karlsruhe, WMC |
| Website | http://www.smart-chips.org |
Description
The overall mission of the 4S project (Smart Chips for Smart Surroundings) is to define and develop efficient (ultra low-power), flexible, reconfigurable core building blocks, including the supporting tools, for future Ambient Systems. The aim is to establish Europe as the dominant player in the field of efficient reconfigurable architectures for ambient devices.
Reconfigurability offers the flexibility and adaptability needed for future ambient devices, it provides the efficiency needed for these systems, it enables systems that can adapt to rapidly changing environmental conditions, it enables communication over heterogeneous wireless networks, and it reduces risks: reconfigurable systems can adapt to standards that may vary from place to place or standards that have changed during and after product development.
It is envisaged that in the long run, work performed within this project will lay the foundations for the development of a new range of ultra low-power components, architectures, tools, guidelines and standards that underpins the future development of Ambient Systems.
Main objectives for the 4S project are:
- The design of a flexible reconfigurable platform based on heterogeneous building blocks such as analogue blocks, hardwired functions, fine and coarse grain reconfigurable tiles, DSPs and microprocessors that can adapt to several algorithms for Ambient Systems without the need for specialized ASICs. The concept is verified on hardware platforms. Furthermore, a digital SoC and an analogue frontend IC will be designed. The DRM (Digital Radio Mondiale) and MPEG4 applications will be implemented on the platform in order to verify the flexibility of the platform.
- To provide a design flow at compile time, which reduces development time and to provide functions that automatically allocate resources of the reconfigurable platform based on Quality of Service, power and user demands. The DRM and MPEG4 applications will verify the design flow.