Project VHD: Introduction to VHDL and VHDL Simulation

This project is a compulsory part of the examination for the System-on-Chip Design course at the University of Twente. The goals of this project are:

The description below refers to various file names. Once you have logged in, execute the command:

get-module vhd vhd

to get them in a subdirectory vhd. If you lose one of the files by mistake, you can re-execute this command. Existing files will not be replaced.

The siso8 circuit that is the topic of this exercise, is presented in a document entitled VHDL for Synthesis and Simulation (also in "Extra Materials"). It is strongly recommended to have read that document before doing any of the exercises.

Exercise VHD-1: Compile and Simulate the copy architecture of siso8

If you are not yet familiar with Modelsim, study the concise manual (also in "Extra Materials") especially written for the students of the University of Twente. In addition, you can consult the tool's help function.

Go to directory vhd that contains the source files, and launch Modelsim. Then, create there a new Modelsim project. Make sure that you copy the library settings from the modelsim.ini file in your current directory (you should do the same for all future projects that you create for this course!). Then, add the following files to the project:

Make sure that the order of the files in the project are as given above and compile them.

Study the file tb_siso8.vhd and pay especially some attention to the architecture behavior of the entity tvc_siso8. You should see that the inputs for the simulation are taken from a file that contains a list of input data. You can modify this file if you want.

Run a simulation and generate waveforms that clearly show that the circuit functions as intended. In this and all future exercises, it is important that you are critical on which signals to trace. Do not blindly include all signals, think of relevant signals in lower levels of the hierarchy, etc. The choices that you make may affect the grade that you will receive. The same is true for the formats of the signals: in some contexts, one prefers to see individual bits, in others signed or unsigned integers, hexadecimal numbers, etc.

Exercise VHD-2: Compile and Simulate the gcd architecture of siso8

Repeat the exercise above for the gcd architecture. In addition to the files mentioned above, you will now need the following files:

Exercise VHD-3: New simple architectures for siso8

Implement the following architectures for siso8:


Deliverables are in hardcopy and should be handed to the assistant. The deliverables for project VHD consist of:


Remark valid for this and future projects: The deliverables as given above are minimum requirements. Having satisfied all deliverable requirements is not necessarily a guarantee for the maximum grade. Some points may be reserved for solutions that are more ingenious or creative than average, for example.
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Last update on: Thu Aug 17 01:30:50 CEST 2017 by Sabih Gerez.