DC Professional (TM) DC Expert (TM) DC Ultra (TM) FloorPlan Manager (TM) HDL Compiler (TM) VHDL Compiler (TM) Library Compiler (TM) DesignWare Developer (TM) DFT Compiler (TM) BSD Compiler Power Compiler (TM) Version A-2007.12-SP3 for suse32 -- Apr 20, 2008 Copyright (c) 1988-2008 by Synopsys, Inc. ALL RIGHTS RESERVED This software and the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software is subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. The above trademark notice does not imply that you are licensed to use all of the listed products. You are licensed to use only those products for which you have lawfully obtained a valid license key. Initializing... dc_shell> dc_shell> Information: Defining new variable 'source_file_list'. (CMD-041) siso_gen_ent.vhd siso_gen_copy_arch.vhd dc_shell> Information: Defining new variable 'top_entity'. (CMD-041) siso_gen dc_shell> Information: Defining new variable 'clock'. (CMD-041) clk dc_shell> Information: Defining new variable 'word_length'. (CMD-041) 16 dc_shell> Information: Defining new variable 'clock_period'. (CMD-041) 5 dc_shell> Information: Defining new variable 'instance'. (CMD-041) siso_gen_copy_16_5 dc_shell> Information: Defining new variable 'insert_scan'. (CMD-041) n dc_shell> Information: Defining new variable 'arch_instance'. (CMD-041) copy_16_5 dc_shell> dc_shell> Information: Variable 'hdlin_enable_presto_for_vhdl' is obsolete and is being ignored. (INFO-100) TRUE dc_shell> dc_shell> dc_shell> Running PRESTO HDLC Compiling Entity Declaration SISO_GEN Presto compilation completed successfully. Loading db file '/opt/Technology/UMC/UMCL18U250D2_2.4/design_compiler/umcl18u250t2_typ.db' Loading db file '/opt/Synopsys/syn/A-2007.12-SP3/libraries/syn/dw_foundation.sldb' Running PRESTO HDLC Compiling Architecture COPY of SISO_GEN Presto compilation completed successfully. Information: Defining new variable 'vhdl_file'. (CMD-041) dc_shell> dc_shell> dc_shell> dc_shell> Loading db file '/opt/Synopsys/syn/A-2007.12-SP3/libraries/syn/gtech.db' Loading db file '/opt/Synopsys/syn/A-2007.12-SP3/libraries/syn/standard.sldb' Loading link library 'umcl18u250t2_typ' Loading link library 'gtech' Running PRESTO HDLC Inferred memory devices in process in routine siso_gen_word_length16 line 22 in file './siso_gen_copy_arch.vhd'. =============================================================================== | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | =============================================================================== | ready_reg | Flip-flop | 1 | N | N | Y | N | N | N | N | | data_out_reg | Flip-flop | 16 | Y | N | Y | N | N | N | N | =============================================================================== Presto compilation completed successfully. Warning: The library named umcl18u250t2_typ specifies a very small trip-point value (0). (TIM-163) Warning: The library named umcl18u250t2_typ specifies a very small trip-point value (0). (TIM-163) Elaborated 1 design. Current design is now 'siso_gen_word_length16'. 1 dc_shell> dc_shell> dc_shell> 1 dc_shell> dc_shell> dc_shell> 1 dc_shell> dc_shell> dc_shell> Current design is 'siso_gen_word_length16'. Information: Renaming design /misc/studaid/soc15/syn/siso_gen_word_length16.db:siso_gen_word_length16 to /misc/studaid/soc15/syn/siso_gen_word_length16.db:siso_gen. (UIMG-45) Current design is 'siso_gen'. 1 dc_shell> dc_shell> dc_shell> dc_shell> FALSE dc_shell> dc_shell> dc_shell> Warning: In design 'siso_gen', output port 'req' is connected directly to 'logic 1'. (LINT-52) Warning: In design 'siso_gen', port 'scan_in' is not connected to any nets. (LINT-28) Warning: In design 'siso_gen', port 'scan_shift' is not connected to any nets. (LINT-28) Warning: In design 'siso_gen', port 'scan_out' is not connected to any nets. (LINT-28) 1 dc_shell> dc_shell> dc_shell> dc_shell> Information: Evaluating DesignWare library utilization. (UISN-27) ============================================================================ | DesignWare Building Block Library | Version | Available | ============================================================================ | Basic DW Building Blocks | A-2007.12-DWBB_0803 | * | | Licensed DW Building Blocks | A-2007.12-DWBB_0803 | | ============================================================================ Information: There are 4 potential problems in your design. Please run 'check_design' for more information. (LINT-99) Beginning Pass 1 Mapping ------------------------ Processing 'siso_gen' Updating timing information Information: Updating design information... (UID-85) Beginning Mapping Optimizations (High effort) ------------------------------- ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- 0:00:02 1398.5 0.00 0.0 0.0 0:00:02 1398.5 0.00 0.0 0.0 0:00:02 1398.5 0.00 0.0 0.0 0:00:02 1398.5 0.00 0.0 0.0 0:00:02 1398.5 0.00 0.0 0.0 0:00:02 1398.5 0.00 0.0 0.0 0:00:02 1398.5 0.00 0.0 0.0 0:00:02 1398.5 0.00 0.0 0.0 Beginning Delay Optimization Phase ---------------------------------- ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- 0:00:02 1398.5 0.00 0.0 0.0 Beginning Area-Recovery Phase (cleanup) ----------------------------- ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- 0:00:03 1398.5 0.00 0.0 0.0 0:00:03 1398.5 0.00 0.0 0.0 0:00:03 1398.5 0.00 0.0 0.0 0:00:03 1398.5 0.00 0.0 0.0 0:00:03 1398.5 0.00 0.0 0.0 0:00:03 1398.5 0.00 0.0 0.0 0:00:03 1398.5 0.00 0.0 0.0 0:00:03 1398.5 0.00 0.0 0.0 0:00:03 1398.5 0.00 0.0 0.0 0:00:03 1398.5 0.00 0.0 0.0 0:00:03 1398.5 0.00 0.0 0.0 Loading db file '/opt/Technology/UMC/UMCL18U250D2_2.4/design_compiler/umcl18u250t2_typ.db' Optimization Complete --------------------- 1 dc_shell> dc_shell> dc_shell> dc_shell> dc_shell> dc_shell> NMA-16 VHDL-286 UCN-4 PWR-18 OPT-932 OPT-317 RCCALC-010 RCCALC-011 dc_shell> 1 dc_shell> 1 dc_shell> dc_shell> 1 dc_shell> dc_shell> dc_shell> hier_copy_16_5 dc_shell> dc_shell> dc_shell> Writing vhdl file '/misc/studaid/soc15/syn/synopsys_out/siso_gen_copy_16_5_hier.vhd'. Warning: A dummy net 'n_1000' is created to connect open pin 'scan_out'. (VHDL-290) 1 dc_shell> dc_shell> dc_shell> **************************************** Report : hierarchy Design : siso_gen Version: A-2007.12-SP3 Date : Thu Sep 2 14:02:16 2010 **************************************** siso_gen DFFRPQL umcl18u250t2_typ INVD1 umcl18u250t2_typ TIEHI umcl18u250t2_typ 1 dc_shell> Information: Updating design information... (UID-85) **************************************** Report : reference Design : siso_gen Version: A-2007.12-SP3 Date : Thu Sep 2 14:02:16 2010 **************************************** Attributes: b - black box (unknown) bo - allows boundary optimization d - dont_touch mo - map_only h - hierarchical n - noncombinational r - removable s - synthetic operator u - contains unmapped logic Reference Library Unit Area Count Total Area Attributes ----------------------------------------------------------------------------- DFFRPQL umcl18u250t2_typ 81.309998 17 1382.269958 n INVD1 umcl18u250t2_typ 8.130000 1 8.130000 TIEHI umcl18u250t2_typ 8.130000 1 8.130000 ----------------------------------------------------------------------------- Total 3 references 1398.529959 1 dc_shell> dc_shell> dc_shell> **************************************** Report : resources Design : siso_gen Version: A-2007.12-SP3 Date : Thu Sep 2 14:02:16 2010 **************************************** No resource sharing information to report. No implementations to report No multiplexors to report 1 dc_shell> dc_shell> dc_shell> Warning: Design has no hierarchy. No cells can be ungrouped. (UID-228) 0 dc_shell> dc_shell> dc_shell> **************************************** Report : reference Design : siso_gen Version: A-2007.12-SP3 Date : Thu Sep 2 14:02:16 2010 **************************************** Attributes: b - black box (unknown) bo - allows boundary optimization d - dont_touch mo - map_only h - hierarchical n - noncombinational r - removable s - synthetic operator u - contains unmapped logic Reference Library Unit Area Count Total Area Attributes ----------------------------------------------------------------------------- DFFRPQL umcl18u250t2_typ 81.309998 17 1382.269958 n INVD1 umcl18u250t2_typ 8.130000 1 8.130000 TIEHI umcl18u250t2_typ 8.130000 1 8.130000 ----------------------------------------------------------------------------- Total 3 references 1398.529959 1 dc_shell> **************************************** Report : timing -path full -delay max -max_paths 1 Design : siso_gen Version: A-2007.12-SP3 Date : Thu Sep 2 14:02:16 2010 **************************************** Operating Conditions: nom_pvt Library: umcl18u250t2_typ Wire Load Model Mode: top Startpoint: data_in(0) (input port) Endpoint: data_out_reg_0_ (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 input external delay 0.00 0.00 f data_in(0) (in) 0.00 0.00 f data_out_reg_0_/D (DFFRPQL) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 5.00 5.00 clock network delay (ideal) 0.00 5.00 data_out_reg_0_/CK (DFFRPQL) 0.00 5.00 r library setup time -0.07 4.93 data required time 4.93 ----------------------------------------------------------- data required time 4.93 data arrival time 0.00 ----------------------------------------------------------- slack (MET) 4.93 1 dc_shell> dc_shell> dc_shell> 1 dc_shell> dc_shell> dc_shell> flat_copy_16_5 dc_shell> dc_shell> dc_shell> Writing vhdl file '/misc/studaid/soc15/syn/synopsys_out/siso_gen_copy_16_5_flat.vhd'. 1 dc_shell> dc_shell> dc_shell> dc_shell> Information: Annotated 'cell' delays are assumed to include load delay. (UID-282) Information: Writing timing information to file '/misc/studaid/soc15/syn/synopsys_out/siso_gen_copy_16_5_flat.sdf'. (WT-3) 1 dc_shell> Thank you...